This invention relates to shift register systems and more particularly to a shift register system using a two phase clock.
Many shift register systems for storing and shifting of binary information are available. The present invention is similar to serial in and serial out shift registers such as the SN7494 or SN7491, components described in the TTL Data book for Design Engineers by Texas Instruments Incorporated (Semiconductor Group) Second Ed, 1976. Such shift registers have been also described in designing texts, such as the Introduction to Digital Computer Design by Herbert S. Schoble, Addison Wesley (1970), which describes the use of shift registers in cyclical shift operations, that is where the output of a serial shift register is connected to the input so that the data will shift cyclically in the shift register. Design of Digital Computers by Hans W. Gschwind and Edward J. McClusky, Springer-Veralag, (1975), describes these types of shift registers as end-around, rotational or circular type shift registers. These types of shift registers have been quite common in modern digital systems for use in examining word masks and other coded information. In addition, circular shift registers are used in arithmetic operations where the preservation of data within the shift register is desired. An earlier version of shift register is disclosed in the U.S. Pat. No. 3,112,411, entitled "Ring Counter Utilizing Bipolar Field Effect Devices" by Charles R. Cook and Gerlad Luecke which disclose an implementation of a device similar to a shift register implemented as a field effect device. U.S. Pat. No. 3,182,295 entitled "Shift Register Device" by Joe B. Clank and William F. Donald, assigned to Texas Instruments Incorporated, discloses an implementation of a shift register device involving the use of magnetic core to provide storage. Another patent, U.S. Pat. No. 3,893,088 entitled, "Random Access Memory Shift Register System", by Anthony G. Bell, assigned to Texas Instruments Incorporated disclosed a random access memory array which is controlled by computator system in order to provide a shift register which has many advantages over the then existing conventional shift register systems. The present invention differs from the prior art in that the object is to store data bits in such a way that they are accessible by different processing units operating at different times. In the preferred embodiment, the use of this invention allows two different central processing units (CPU) to use the same registers and the same data paths independent of the operation of each other. That is, according to one phase, one CPU can use a single storage register to contain data and use that data in operations combined with an arithmetic logic unit and memory. While independent of the first central processing unit, a second central processing unit can use the same register in such a way that data stored in that register is independent of data stored in that same register by the first CPU thus allowing the second CPU to operate on data that the second CPU stored in the register but the same arithmetic logic unit and memory.